library IEEE;
use ieee.std_logic_1164.all;

package package_sumador is
	component cont_ceros_significativos is
	port(entrada		: IN	std_logic_vector(7 downto 0);
		 salida			: OUT	integer
		 );
	end component;
	
	component desplazador is
	port(entrada		: IN		std_logic_vector(7 downto 0);
		  direccion		: IN		std_logic;
		  cantidad		: IN		integer;
		  salida		: OUT		std_logic_vector(7 downto 0)
		);
	end component;
	
	component selector_fraccion is
	port(
		 a, b	: in std_logic_vector (7 downto 0);
		 sel	: in std_logic;
		 out1, out2	: out std_logic_vector(7 downto 0)
		 );
	end component;
	
	component sum_exp is

	port (
		p, q: in std_logic_vector(7 downto 0);
		r	: out std_logic_vector(7 downto 0);
		t	: out integer;
		z	: out std_logic
		);
	end component;
	
	component reg_8 is
	port(a		  : in	std_logic_vector (7 downto 0);
		 clk, rst : in   std_logic;
		 z	 	  : out	std_logic_vector (7 downto 0)
		 );
	end component;
end package_sumador;
